Currently, the highest breakdown voltages achieved by silicon power devices range from 4.5 to 6.5 kV for IGBTS and GTOs, and 9 to 12 kV for thyristors. The ability of these switching devices to handle higher voltages is today limited by technological factors, such as requirements of serial operations, and by the physical properties of the silicon semiconductor. It is considered that higher voltage (>10 kV) electrical transmission systems would benefit from the higher critical electrical field of the wider band-gap silicon carbide semiconductor. In addition, for an equivalent voltage rating, silicon carbide devices offer the advantages of lower on state resistances and lower switching losses than their silicon counterparts.
An example structure according to the prior art, comprising a lightly doped voltage blocking layer 3 deposited on a SIC substrate 1 is illustrated in FIG. 1. At present, all such voltage supporting SIC layers are epitaxially grown on highly doped off-oriented SiC substrates 1. The established method for growing such layers 3 is the CVD technique carried out at temperatures around 1600° C. The advantage of the CVD technique lies in its ability to meet the low n- or p-type doping (typically 1015 cm−3 range and lower) and the high carrier lifetime (several hundreds of nanoseconds) requirements needed for SIC bipolar devices. The main disadvantage of the CVD process lies In its low growth rate and thus high cost for layers thicker than 100 μm. For example, at a growth rate ranging between 5 and 10 μm/h, a 250 μm thick drift zone for a 20 kV blocking layer at ND˜3×1014 cm−3, the existing CVD processes require growth times as long as 25 to 50 hours.
In the silicon technology, the high cost of epitaxial power device structures has been tackled by using, instead of a thick low doped epilayer grown on a conductive substrate, a low doped silicon wafer as drift zone. The starting Wafers for state-of-the-art high power silicon devices are 4 to 6 inch diameter neutron transmuted wafers manufactured from float-zone grown SI crystals. For example, the drift region of a 5 kV switching device uses an approximately 500 μm thick silicon wafer with a doping of 2×10−3.
This technology presently limits silicon power devices to voltage handling capabilities to the 10 kV range. A 25 kV silicon device would require the use of a wafer 2 mm thick as drift zone with a doping of 1012 cm−3 or less and a carrier lifetime of 400 μs. A silicon carbide switching device would use an order of magnitude thinner drift zone, one to two orders of magnitude higher doping and lower carrier lifetime to achieve the same blocking voltage, while offering the advantages of a lower on state resistance and lower switching losses.
This approach can however not be used with the present state-of-the-art silicon carbide wafers due to the lack of lightly doped, microsecond range lifetime, SIC wafers. SIC wafers are presently available for the use as substrates in the lower range resistivity (n-type, ca. 0.015 Ωcm and p-type ca. 2.5 Ωcm) and in semi-insulating form (p>106 Ωcm). For the low resistivity substrates, the shallow dopants concentrations (e.g. nitrogen or aluminium) are typically in the 1016 cm−3 range or higher, whereas semi-insulating substrates contain a higher density of deep levels (intrinsic or extrinsic) than shallow levels (e.g. nitrogen). Neither a low resistivity substrate, which has no reverse voltage supporting capability, nor a semi-insulating substrate, where the free carriers lifetime is less than a few nanoseconds, can thus be used as a drift zone for power devices.
Vertical SIC semiconductor power devices fabricated on “low resistivity” p-type substrates exist up to now only In theory since a suitable base material with sufficient conductivity is not available (approx. 8 Ωcm vs. 0.02 Ωcm for n-type material). The reason for this lack can be attributed to the current technology of the most common crystal growth process. The incorporation of aluminum is hard to control In sublimation growth furnaces especially in the case of high doping concentrations. Additionally the ionization energy of all known acceptors in silicon carbide is comparably high. Thus, it is not possible to fabricate an attractive IGBT like structure using a p-type substrate with a n-type drift zone grown by epitaxy. Additionally, also assuming the availability of a suited base material, there are only restricted possibilities to adjust device parameters by lifetime modulation near the backward emitter of a deduced IGBT structure (FIG. 1).
Up to know, the realized IBGT structures on epitaxied SiC substrates suffer from unsatisfactory technical parameters. In all cases, the base material was p-type with a very low conductivity. The successful realization of a classical IGBT structure using a MOS Gate seems not to be possible, since in this case the oxide stress is very high and the reliability will be strongly degraded (except using adequate shielding precautions).